This invention relates to an LVDS interface, incorporating phase-locked loop circuitry, for use in a programmable logic device. More particularly, this invention relates to an LVDS interface having a phase-locked loop circuit to control the shifting of data at high speeds.
Programmable logic devices are well known. Commonly, a programmable logic device has a plurality of substantially identical logic elements, each of which can be programmed to perform certain desired logic functions. The logic elements have access to a programmable interconnect structure that allows a user to interconnect the various logic elements in almost any desired configuration. Finally, the interconnect structure also provides access to a plurality of input/output (xe2x80x9cI/Oxe2x80x9d) pins, with the connections of the pins to the interconnect structure also being programmable.
At one time, programmable logic devices of the type just described were implemented almost exclusively using transistor-transistor logic (xe2x80x9cTTLxe2x80x9d), in which a logical xe2x80x9chighxe2x80x9d signal was nominally at 5 volts, while a logical xe2x80x9clowxe2x80x9d signal was nominally at ground potential, or 0 volts. More recently, however, other logic standards have come into general use, some of which use different signalling schemes, such as LVTTL (Low Voltage TTL), PCI (Peripheral Component Interface), SSTL (Series Stub Terminated Logic, which has several variants), GTL (Gunning Transceiver Logic) or GTL+, HSTL (High Speed Transceiver Logic, which has several variants), LVDS (Low Voltage Differential Signalling), and others. Some of these signalling schemes, and particularly LVDS, require high-frequency clock signals with precise phase relationships for proper operation.
It is known to include phase-locked loop circuitry on programmable logic devices to help counteract xe2x80x9cskewxe2x80x9d and excessive delay in clock signals propagating on the device (see, for example, Jefferson U.S. Pat. No. 5,699,020 and Reddy et al. U.S. Pat. No. 5,847,617, both of which are hereby incorporated by reference herein in their entireties). For example, phase-locked loop circuitry may be used to produce a clock signal which is advanced in time relative to a clock signal applied to the programmable logic device. The advanced clock signal is propagated to portions of the device that are relatively distant from the applied clock signal so that the propagation delay of the advanced clock signal brings it back into synchronism with the applied clock signal when it reaches the distant portions of the device. In this way all portions of the device receive synchronous clock signals and clock signal xe2x80x9cskewxe2x80x9d (different amounts of delay in different portions of the device) is reduced.
However, while phase-locked loops are accurate sources of clock signals, they generally are limited in the frequencies they can provide, both in terms of adjustability, and in terms of the absolute range of frequencies that can be generated. This has limited the speed of LVDS interfaces.
It would be desirable to be able to provide an LVDS interface for a programmable logic device, which interface includes a phase-locked loop circuit for accurate input/output timing.
It is an object of this invention to attempt to provide an LVDS interface for a programmable logic device, which interface includes a phase-locked loop circuit for accurate input/output timing.
In accordance with the present invention, there is provided an LVDS input interface for a programmable logic device having a plurality of signal conductors. The LVDS interface includes a pair of input terminals for accepting an input LVDS signal, and an LVDS differential input driver for converting the input LVDS signal into a data signal comprising a serial stream of data bits. A number of shift registers are provided, having a shift register input for accepting the serial stream of data bits, and each of the shift registers has a shift register output. The same number of second registers are also provided, each register in that number of second registers having an input coupled to one of the shift register outputs and having a registered output coupled to one of the signal conductors. An input phase-locked loop circuit generates first and second input clock signals having first and second input clock rates, with the first input clock rate being a multiple of the second input clock rate, where the multiple is an integer that at most equals that number. The first input clock signal controls shifting of the serial stream of data bits into the first shift registers, and the second input clock signal controls registration of the data bits from the inputs of the second registers to the outputs of the second registers. On each one cycle of the second clock signal, (a) an existing set of that multiple of data bits previously applied in parallel by the shift register outputs to the inputs of the second registers are registered to the outputs of the second registers for conduction in parallel onto the signal conductors, and (b) the first input clock signal goes through that multiple of cycles, clocking a new set of that number of data bits into the shift registers, whence they are conducted to the inputs of the second registers.
An LVDS output interface for the programmable logic device is also provided, and includes a number of first registers, each register in that number of first registers having an input coupled to one of the signal conductors and having a registered output. That number of shift registers is also provided, each shift register in that number of shift registers having an input coupled to one of the registered outputs, and the shift registers having a shift register output for providing a serial stream of data bits. An output phase-locked loop circuit generates first and second output clock signals having first and second output clock rates. The second output clock rate is a multiple of the first output clock rate, where the. multiple is an integer at most equal to that number. An LVDS differential output driver converts the serial stream of data bits into an output LVDS signal, which is conducted to a pair of output terminals. The first output clock signal controls registration-of the data bits from the inputs of the first registers to the registered outputs, whence they are conducted to the inputs of the shift registers. The second output clock signal controls shifting of the data bits out of the shift registers as the serial stream of data bits. On each one cycle of said first output clock signal, (a) the second output clock signal goes through that multiple of cycles, clocking a set of that multiple of data bits out the shift registers as the serial stream of data bits, and (b) an existing set of that multiple of data bits previously conducted by the signal conductors into the first registers are registered to the registered outputs. of the first registers whence they are conducted in parallel to the shift registers, while a new set of that multiple of data bits are conducted into the inputs of the first registers by the signal conductors.
The input and output phase-locked loop circuits allow high speed LVDS operation by providing accurate, synchronized clock signals that allow a selected number of bits to be clocked between a shift register chain and a set of parallel registers. It is readily understood that the clock that controls the clocking of data serially into or out of the shift registers must be an exact multiple of the clock that controls the clocking of data in parallel mode into or out of the shift registers. If the serial clock runs too slowly, not all of the serial data will be clocked into or out of the shift registers before the next parallel transfer of data. Similarly, if the serial clock runs too quickly, the system will attempt to clock more data than are available into or out of the shift registers before the next parallel transfer occurs. On the input side, the system will attempt to clock more data into the shift registers before the system is ready to transfer it into the programmable logic device in parallel, with the result that some of the data already in the shift registers may be clocked out too soon and be lost. Similarly, on the output side, the system may attempt to clock data out of the shift registers to provide serial output of the programmable logic device even before the data have been transferred in parallel from the programmable logic device to the shift registers, with the result that the output data stream will contain gaps or erroneous data.
The present invention avoids these difficulties by providing specialized, dedicated high-speed phase-locked loop-based clocks specifically for use with high-speed LVDS interfaces. The clock signals are provided elsewhere on the device to the extent that they may be required in connection with use of the LVDS data, but the clocks are not intended for general use. Other phase-locked loop-based clocks are provided that are meant for general use. Those other clocks are adjustable and are described in copending, commonly assigned U.S. patent application Ser. Nos. 60/115,238, filed Jan. 8, 1999 and U.S. Pat. application Ser. No. 09/366,940, filed Aug. 4, 1999. Unlike those clocks, however, the clocks according to present invention are built for accuracy, with no adjustable components provided that might give rise to inaccuracies, as described below.
A phase-locked loop-based clock circuit according to the invention preferably is provided with a programmable, or loadable, xe2x80x9cdivide-by-Wxe2x80x9d feedback-scale counter in its feedback loop. This allows the clock circuit to provide two clock outputsxe2x80x94a first output at a lower frequency, and a second output at a higher frequency, equal to W times the lower frequency, with the two clock outputs in phase-locked relationship, either with or without a predetermined on-zero phase shift, as described below. If W is the number of bits of data transferred in parallel (i.e., the xe2x80x9cwordxe2x80x9d size), this allows an entire word to be clocked serially into or out of an input or output shift register chain under the control of the high-speed clock precisely in the time it takes to transfer the word in parallel between the logic of the programmable logic device and the shift register chain, preventing the loss of data that might result if the clocks were not substantially perfectly synchronized.